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atwilc1000b - mut ieee 802.11 b/g/n link controller soc datasheet description atmel ? atwilc1000b is a single chip ieee ? 802.11 b/g/n radio/baseband/mac link controller optimized for low - power mobile applications. atwilc1000b supports single stream 1x1 802.11n mode providing up to 72mbps phy rate. the atwilc1000b features fully integrated power amplifier, lna, switch , and power management. implemented in 65nm cmos technology, the atwilc1000b offers very low power co nsumption while simultaneously providing high performance and minimal bill of materials. the atwilc1000b supports 2 - and 3 - wire bluetooth ? coexistence protocols. the atwilc1000b provides multiple peripheral interfaces including uart, spi, i 2 c, and sdio. th e only external clock source needed for the atwilc1000b is a high - speed crystal or oscillator with a wide range of reference clock frequencies supported (12 - 40mhz). the atwilc1000b is available in both qfn and wafer level chip scale package (wlcsp) packagi ng. features ? ie ee 802. 1 b/g/n 20mhz (1x1) solution ? single spatial stream in 2.4ghz ism band ? integrated pa and t/r switch ? superior sensitivity and range via advanced phy signal processing ? advanced equalization and channel estimation ? advanced carrier and tim ing synchronization ? wi - fi direct and soft - ap support ? supports ieee 802.11 wep, wpa, and wpa2 security ? supports china wapi security ? superior mac throughput via hardware accelerated two - level a - msdu/a - mpdu frame aggregation and block acknowledgement ? on - chip memory management engine to reduce host load ? spi, sdio, uart, and i 2 c host interfaces ? 2 - or 3 - wire bluetooth coexistence interface ? operating temperature range of - 40c to +85c ? power save modes: C <1a power down mode typical @3.3v i/o C 3 80 a doze mode with c hip settings preserved (used for beacon monitoring) C on - chip low power sleep oscillator C fast host wake - up from doze mode by a pin or host i/o transaction atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 2 2 ta bl e of conte nts 1 ordering information and ic marking ................................ ................................ ........ 4 2 block diagram ................................ ................................ ................................ ............. 4 3 pinout and package information ................................ ................................ ................ 4 3.1 pin description ................................ ................................ ................................ ................................ ...... 4 3.2 package description ................................ ................................ ................................ ............................. 7 4 elec trical specifications ................................ ................................ ........................... 11 4.1 absolute ratings ................................ ................................ ................................ ................................ . 11 4.2 recommended operating conditions ................................ ................................ ................................ . 11 4.3 dc electrical characteristics ................................ ................................ ................................ ............... 12 5 clocking ................................ ................................ ................................ ................... 13 5.1 crystal oscillator ................................ ................................ ................................ ................................ . 13 5.2 low - power oscillator ................................ ................................ ................................ .......................... 14 6 cpu and memory subsystems ................................ ................................ ................. 15 6.1 processor ................................ ................................ ................................ ................................ ............ 15 6.2 memory sub system ................................ ................................ ................................ ............................. 15 6.3 non - volatile memory (efuse) ................................ ................................ ................................ .............. 15 7 wlan subsystem ................................ ................................ ................................ ...... 16 7.1.1 features ................................ ................................ ................................ ................................ . 16 7.1.2 descript ion ................................ ................................ ................................ .............................. 16 7.2 phy ................................ ................................ ................................ ................................ .............. 17 7.2.1 features ................................ ................................ ................................ ................................ . 17 7.2.2 description ................................ ................................ ................................ .............................. 17 7.3 radio ................................ ................................ ................................ ................................ .............. 17 7.3.1 receiver performance ................................ ................................ ................................ ............ 17 7.3.2 transmitter performance ................................ ................................ ................................ ........ 19 8 external interfaces ................................ ................................ ................................ .... 20 8.1 i 2 c slave interface ................................ ................................ ................................ .............................. 20 8.2 i 2 c master interface ................................ ................................ ................................ ............................ 21 8.3 spi slave interface ................................ ................................ ................................ .............................. 22 8.4 spi master interface ................................ ................................ ................................ ............................ 24 8.5 sdio slave interface ................................ ................................ ................................ ........................... 25 8.6 uart ................................ ................................ ................................ ................................ .............. 27 8.7 wi - fi/bluetoot h coexistence ................................ ................................ ................................ ............... 28 8.8 gpios ................................ ................................ ................................ ................................ .............. 28 9 power management ................................ ................................ ................................ ... 29 9.1 power architecture ................................ ................................ ................................ .............................. 29 9.2 power consumption ................................ ................................ ................................ ............................ 30 9.2.1 description of device states ................................ ................................ ................................ ... 30 9.2.2 current consumption in various device states ................................ ................................ ...... 30 9.2.3 restrictions for power states ................................ ................................ ................................ . 31 9.3 power - up/down sequence ................................ ................................ ................................ ................. 31 9.4 digital i/o pin behavior during power - up sequences ................................ ................................ ......... 32
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 3 3 10 reference design ................................ ................................ ................................ ...... 33 11 reflo w profile information ................................ ................................ ........................ 34 11.1 storage condition ................................ ................................ ................................ ................................ 34 11.1.1 moisture barrier bag before opened ................................ ................................ ..................... 34 11.1.2 moisture barrier bag open ................................ ................................ ................................ ..... 34 11.2 stencil design ................................ ................................ ................................ ................................ ..... 34 11.3 baking conditions ................................ ................................ ................................ ............................... 34 11.4 soldering and reflow condition ................................ ................................ ................................ .......... 34 11.4.1 reflow oven ................................ ................................ ................................ ........................... 34 12 reference documentation and support ................................ ................................ ... 36 12.1 reference documents ................................ ................................ ................................ ......................... 36 13 revision history ................................ ................................ ................................ ........ 37
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 4 4 1 ordering information and ic marking table 1 - 1. ordering details atmel o fficial p art n umber (for ordering) p ackage t ype ic m arking atwilc1000b - mu - t 5x5 qfn in tape and reel atwilc1000b atwilc1000b - uu - t 3.25x3.25 wlcsp in tape and reel atwilc1000b 2 block diagram figure 2 - 1. atwilc1000b block diagram 3 pino ut and package information 3.1 pin description atwilc1000b is offered in an exposed pad 40 - pin qfn package. this package has an exposed paddle that must be connected to the system board ground. the qfn package pin assignment is shown in figure 3 - 1 . the color shading is used to in dicate the pin type as follows: ? green C power ? red C analog ? blue C digital i/o ? yellow C digital input ? grey C unconnected or reserved the atwilc1000b pins are described in table 3 - 1 . x x t x d i g i t a l c o r e d p d 8 0 2 . 1 1 b g n i f f t 8 0 2 . 1 1 b g n c o d i n g h o s t i n t e r f a c e m i c r o c o n t r o l l e r d a c a d c r x d i g i t a l c o r e 8 0 2 . 1 1 b g n o f d m c h a n n e l e s t i m a t i o n / e q u a l i z a t i o n 8 0 2 . 1 1 b g n f o r w a r d e r r o r c o r r e c t i o n r a m p l l 8 0 2 . 1 1 b g n m a c ~ s d i o s p i b l u e t o o t h c o e x i s t a n c e x o p m u r t c c l o c k v b a t t u a r t x 2 g p i o i 2 c w i l c 1 0 0 0 b
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 5 5 figure 3 - 1. pin assignment table 3 - 1. pin description pin # pin name pin type description 1 tp_p a nalog test pin/customer no connect 2 vdd_rf_rx power tuner rf supply (see section 9.1 ) 3 vdd_ams power t uner bb supply (see section 9.1 ) 4 vdd_rf_tx power tuner rf supply (see section 9.1 ) 5 vdd_batt_ppa power pa 1st stage supply (see section 9.1 ) 6 vdd_batt_pa power pa 2nd stage supply (see section 9.1 ) 7 rfiop analog pos . rf differential i/o (see table 9 - 3 ) 8 rfion analog neg . rf differential i/o (see table 9 - 3 ) 9 sdio_spi_cfg digital input tie to 1 for spi, 0 for sdio 10 gpio0/host_wake digital i/o, programmable pull - up gpio0/sleep mode control 11 gpio2/irqn digital i/o, programmable pull - up gpio2/device interrupt 12 sd_dat3 digital i/o, programmable pull - up sdio data3
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 6 6 pin # pin name pin type description 13 sd_dat2/spi_rxd digital i/o, programmable pull - up sdio data2/spi data rx 14 vddc power digital core power supply (see section 9.1 ) 15 vddio power digita l i/o power supply (see section 9.1 ) 16 sd_dat1/spi_ssn di gital i/o, programmable pull - up sdio data1/spi slave select 17 sd_dat0/spi_txd digital i/o, programmable pull - up sdio data0/spi data tx 18 sd_cmd/spi_sck digital i/o, programmable pull - up sdio command/spi clock 19 sd_clk digital i/o, programmable pull - up sdio clock 20 vbatt_buck power battery supply f or dc/dc converter (see sec- tion 9.1 ) 21 vsw power switching output of dc/dc converter (see section 9.1 ) 22 vreg_buck power core power fr om dc/dc converter (see sec- tion 9.1 ) 23 chip_en analog pmu enable 24 gpio1/rtc_clk digital i/o, programmable pull - up gpio1/32khz clock input 25 test_mode digital input test mode C customer tie to gnd 26 vddio power digita l i/o power supply (see section 9.1 ) 27 vddc power digital core power supply (see section 9.1 ) 28 gpio3 digital i/o, programmable pull - up gpio3/spi_sck_flash 29 gpio4 digital i/o, programmable pull - up gpio4/spi_ssn_flash 30 gpio5 digital i/o, programmable pull - up gpio5/spi_txd_flash 31 gpio6 digital i/o, programmable pull - up gpio6/spi_rxd_flash 32 i2c_scl digital i/o, programmable pull - up i2c slave clock (high - drive pad, see table 4 - 3 ) 33 i2c_sda digital i/o, programmable pull - up i2c slave data (high - drive p ad, see table 4 - 3 ) 34 resetn digital input active - low hard reset 35 xo_n analog crystal oscillator n 36 xo_p analog crystal oscillator p 37 vdd_sxdig power sx power supply (see section 9.1 ) 38 vdd_vco power vco power supply (see section 9.1 ) 39 vddio_a power tuner vddio power supply (see section 9.1 ) 40 tpn analog test pin/customer no connect 41 (1) paddle vss power connect to system board ground notes: 1. applies to qfn package only.
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 7 7 3.2 package description the atwilc1000b qfn package information is provided in table 3 - 2 . table 3 - 2. qfn package information parameter value units tolerance package size 5x5 mm 0.1mm qfn pad count 40 total thickness 0.85 mm 0.05mm qfn pad pitch 0.40 pad width 0.20 exposed pad size 3.7x3.7 the atwilc1000b 40l qfn package view is shown in figure 3 - 2 .
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 8 8 figure 3 - 2. qfn package the qfn package is a qualified green package.
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 9 9 figure 3 - 3. wlcsp package
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 1 0 10 figure 3 - 4. wlcsp wilc1000b uu
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 1 1 11 4 electrical specifications 4.1 absolute ratings table 4 - 1. absolute maximum ratings characteristic symbol min . max . unit core supply voltage vddc - 0.3 1.5 v i/o supply voltage vddio - 0.3 5.0 battery supply voltage vbatt - 0.3 5.0 digital input voltage v in - 0.3 vddio analog input voltage v ain - 0.3 1.5 esd human body model v esdhbm - 1000, - 2000 (see notes below) +1000, +2000 (see notes below) storage temperature t a - 65 150 oc junction temperature 125 rf input power max 23 dbm notes: 1. v in corresponds to all the digital pins. 2. v ain corresponds to the following analog pins: vdd_rf_rx, vdd_rf_tx, vdd_ams, rfiop, rfion, xo_n, xo_p, vdd_sxdig, vdd_vco. 3. for v esdhbm , each pin is classified as class 1, or class 2, or both: ? the class 1 pins include all the pins (both analog and digital) ? the class 2 pins are all digital pins only ? v esdhbm is 1kv for class1 pins. v esdhbm is 2kv for class2 pins 4.2 recommended operating conditions table 4 - 2. recommended operating conditions characteristic symbol min . typ . max . unit i/o supply voltage low range vddio l 1.62 1.80 2.00 v i/o supply voltage mid - range vddio m 2.00 2.50 3.00 i/o supply voltage high range vddio h 3.00 3.30 3.60 battery supply voltage vbatt 2.5a 3.60 4.20 operating temperature - 40 85 oc notes: 1. atwilc1000b is functional across this range of voltages; however, optimal rf performance is guaranteed for vbatt in the range 3.0v < vbatt < 4.2v . 2. i/o supply voltage is applied to the following pins: vddio_a, vddio. 3. battery supply voltage is applied to following pins : vdd_batt_ppa, vdd_batt_pa, vbatt_buck. 4. refer to section 9.1 and table 9 - 3 for the details of power connections.
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 1 2 12 4.3 dc electrical characteristics table 4 - 3 provides the dc cha racteristics for the atwilc1000b digital pads . table 4 - 3. dc electrical characteristics vddio c ondition characteristic min . typ . max . unit vddio l input low voltage v il - 0.30 0.60 v input high voltage v ih vddio - 0.60 vddio+0.30 output low voltage v ol 0.45 output high voltage v oh vddio - 0.50 vddio m input low voltage v il - 0.30 0.63 input high voltage v ih vddio - 0.60 vddio+0.30 output low voltage v ol 0.45 output high voltage v oh vddio - 0.50 vddio h input low voltage v il - 0.30 0.65 input high voltage v ih vddio - 0.60 vddio+0.30 (up to 3.60) output low voltage v ol 0.45 output high voltage v oh vddio - 0.50 all output loading 20 pf all digital input load 6 vddio l p ad drive strength (regular pads (1) ) 1.7 2.4 ma vddio m p ad drive strength (regular pads (1) ) 3.4 6.5 vddio h pad drive strength (regular pads (1) ) 10.6 13.5 vddio l pad drive strength (high - drive pads (1) ) 3.4 4.8 vddio m pad drive strength (high - drive pads (1) ) 6.8 13 vddio h pad drive strength (high - drive pads (1) ) 21.2 27 note: 1. the following are high - drive pads: i2c_scl, i2c_sda; all other pads are regular .
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 1 3 13 5 clocking 5.1 crystal oscillator table 5 - 1. crystal oscillator parameters parameter min . typ . max . unit crystal resonant frequency 12 26 40 mhz crystal equivalent series resistance 50 150 ? stability C initial offset (1) - 100 100 ppm stability - temperature and aging - 25 25 note: 1. initial offset must be calibrated to maintain 25ppm in all operating conditions. this calibration is performed during final production testing . the block diagram in figure 5 - 1 (a) shows how the internal crystal oscillator (xo) is connected to the external crystal. the xo has 5pf internal capacitance on each terminal xo_p and xo_n. to bypass the crystal oscillator wi th an external reference, an external signal capable of driving 5pf can be applied to the xo_n terminal as shown figure 5 - 1 (b) . figure 5 - 1. xo connections (a) crystal oscillator is used b) crystal oscillator is bypassed table 5 - 2 specifies the electrical and performance requirements for the external clock . table 5 - 2. bypass clock specification parameter min . max . unit comments oscillation frequency 12 32 mhz must be able to drive 5pf load @ desired fre- quency voltage swing 0.5 1.2 vpp must be ac coupled stability C temperature and aging - 25 +25 ppm phase noise - 130 dbc/hz at 10khz offset jitter (rms) <1psec based on integrated phase noise spectrum from 1khz to 1mhz a t w i l c 1 0 0 0 b x o _ n x o _ p ( a ) a t w i l c 1 0 0 0 b x o _ n x o _ p ( b ) e x t e r n a l c l o c k
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 1 4 14 5.2 low - power oscillator atwilc1000b has an internally - generated 32khz clock to provide timing information for various sleep functions. alternatively, atwilc1000b allows for an external 32khz clock to be used for this purpose, which is provided through pin 24 (rtc_clk). software selects whether the internal clock or external clock is used. the internal low - power clock is ring - oscillator based and has accuracy within 10,000ppm. when using the internal low - power clock, the advance wakeup time in beacon monitoring mode has to be increased by about 1% of the sleep time to compensate for the oscillator inaccuracy. for example, for the dtim interval value of 1, wakeup time has to be increased by 1ms. for any application targeting very low power consumption, an externa l 32khz rtc clock should be used.
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 1 5 15 6 cpu and memory subsystems 6.1 processor atwilc1000b has a cortus aps3 32 - bit processor. this processor performs many of the mac functions, including but not limited to association, authentication, power management, security key management, and msdu aggregation/de - aggregation. in addition, the processor provides flexibility for various modes of operation, such as sta and ap modes . 6.2 memory subsystem the aps3 core us es a 128 kb instru ction/boot rom along with a 160 kb instruction r am and a 64kb data ram. in addition, the device uses a 128 kb shared ram, accessible by the processor and mac, which allows the aps3 core to perform various data management tasks on the tx and rx data packets . 6.3 non - v olatile memory (e fuse) atwilc1000b has 768 bits of non - volatile e fuse memory that can be read by the cpu after device reset. this non - volatile one - time - programmable (otp) memory can be used to store customer - specific parameters, such as mac address; various calibration information, such as tx powe r , crystal frequency offset, etc . ; and other software - specific con figuration parameters. the e fuse is partitioned into six 128 - bit banks. each bank has the same bit map, which is shown in fig ure 6 - 1 . the purpose of the first 80 bits in each bank is fixed, and the remaining 48 bits are general - purpose software dependent bits, or reserved for future use. since each bank can be programmed i ndependently, this allows for several updates of the device parameters fo llowing the initial programming e.g. , updating mac address. r efer to atwilc1000b programming guide for the e fuse programming instructions . figure 6 - 1. e fuse bit map b a n k 0 b a n k 1 b a n k 2 b a n k 3 b a n k 4 b a n k 5 f m a c a d d r u s e d i n v a l i d v e r s i o n r e s e r v e d m a c a d d r u s e d f o f l a g s g 3 1 1 4 1 u s e d t x g a i n c o r r e c t i o n u s e d f r e q . o f f s e t 1 7 4 8 8 8 1 6 1 1 5 1 2 8 b i t s
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 1 6 16 7 wlan subsystem the wlan subsystem is composed of the media access controller (mac) and the physical layer (phy). the following two subsections describe the mac and phy in detail . 7.1.1 features the atwilc1000b ieee802.11 mac supports the following functions : ? ie ee 802.11b/g/n ? ieee 802.11e wmm qos edca/pcf multiple access categories traffic scheduling ? advanced ieee 802.11n features: C transmission and recepti on of aggregated mpdus (a - mpdu) C transmission and reception of aggregated msdus (a - msdu) C immediate block acknowledgement C reduced interframe spacing (rifs) ? support for ieee 802.11i and wfa security with key management C wep 64/128 C wpa - tkip C 128 - bit wpa2 ccmp (aes) ? support for wapi security ? advanced power management C standard 802.11 power save mode C wi - fi alliance w mm - ps (u - apsd) ? rts - cts and cts - self support ? supports either sta or ap mode in the infrastructure basic service set mode ? supports independent basic service set (ibss) 7.1.2 description the atwilc1000b mac is designed to operate at low power while providing high d ata throughput. the ieee 802.11 mac functions are implemented with a combination of dedicated datapath engines, hardwired control logic, and a low - power, high - efficiency microprocessor. the combination of dedicated logic with a programmable processor provi des optimal power efficiency and real - time response while providing the flexibility to accommodate evolving standards and future feature enhancements. dedicated datapath engines are used to implement data path functions with heavy computational requirement s. for example, a fcs engine checks the crc of the transmitting and receiving packets, and a cipher engine performs all the required encryption and decryption operations for the wep, wpa - tkip, wpa2 ccmp - aes, and wapi security requirements. control function s which have real - time requirements are implemented using hardwired control logic modules. these logic modules offer real - time response while maintaining configurability via the processor. examples of hardwired control logic modules are the channel access control module (implements edca/hcca, beacon tx control, interframe spacing, etc.), protocol timer module (responsible for the network access vector, back - off timing, timing synchronization function, and slot management), mpdu handling module, aggregation/ de - aggregation module, block ack controller (implements the protocol requirements for burst block communication), and tx/rx control fsms (coordinate data movement between phy - mac interface, cipher engine, and the dma interface to the tx/rx fifos).
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 1 7 17 the ma c functions implemented solely in software on the microprocessor have the following characteristics: ? functions with high memory requirements or complex data structures. examples are association table management and power save queuing. ? functions with low co mputational load or without critical real - time requirements. examples are authentication and association. ? functions which need flexibility and upgradeability. examples are beacon frame processing and qos scheduling. 7.2 phy 7.2.1 features the atwilc1000b ieee802.11 phy supports the following functions: ? single antenna 1x1 stream in 20mhz channels ? supports ieee 802.11b dsss - cck modulation: 1, 2, 5.5, 11mbps ? supports ieee 802.11g ofdm modulation: 6, 9, 12,18, 24, 36, 48, 54mbps ? supports ieee 802.11n ht modul ations mcs0 - 7, 20mhz, 800 and 400ns guard interval: 6.5, 7.2, 13.0, 14.4, 19.5, 21.7, 26.0, 28.9, 39.0, 43.3, 52.0, 57.8, 58.5, 65.0, 72.2mbps ? ieee 802.11n mixed mode operation ? per packet tx power control ? advanced channel estimation/equalization, automatic gain control, cca, carrier/symbol recovery, and frame detection 7.2.2 description the atwilc1000b wlan phy is designed to achieve reliable and power - efficient physical layer communi cation specified by ieee 802.11 b/g/n in single stream mode with 20mhz bandwidth. advanced algorithms have been employed to achieve maximum throughput in a real world communication environment with impairments and interference. the phy implements all the required functions such as fft, filtering, fec (viterbi decoder), frequency and ti ming acquisition and tracking, channel estimation and equalization, carrier sensing and clear channel assessment, as well as the automatic gain control . 7.3 radio 7.3.1 receiver performance radio performance under typical conditions: vbat t =3.6v; vddio=3.3v; t emp . : 2 5c . table 7 - 1. receiver performance parameter description min . typ . max . unit frequency 2,412 2,484 mhz sensitivity 802.11b 1mbps dss - 98 dbm 2mbps dss - 94 5.5mbps dss - 92 11mbps dss - 88 sensitivity 802.11g 6mbps ofdm - 90 dbm 9mbps ofdm - 89
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 1 8 18 parameter description min . typ . max . unit 12mbps ofdm - 88 18mbps ofdm - 85 24mbps ofdm - 83 36mbps ofdm - 80 48mbps ofdm - 76 54mbps ofdm - 74 sensitivity 802.11n (bw=20mhz) mcs 0 - 89 dbm mcs 1 - 87 mcs 2 - 85 mcs 3 - 82 mcs 4 - 77 mcs 5 - 74 mcs 6 - 72 mcs 7 - 70.5 maximum receive signal level 1 - 11mbps dss - 10 0 dbm 6 - 54mbps ofdm - 10 0 mcs 0 C 7 - 10 0 adjacent channel rejection 1mbps dss (30mhz offset) 50 db 11mbps dss (25mhz offset) 43 6mbps ofdm (25mhz offset) 40 54mbps ofdm (25mhz offset) 25 mcs 0 C 20mhz bw (25mhz offset) 40 mcs 7 C 20mhz bw (25mhz offset) 20 cellular blocker immunity 776 - 794mhz cdma - 14 dbm 824 - 849mhz gsm - 10 880 - 915mhz gsm - 10 1710 - 1785mhz gsm - 15 1850 - 1910mhz gsm - 15 1850 - 1910mhz wcdma - 24 1920 - 1980mhz wcdma - 24
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 1 9 19 7.3.2 transmitter performance radio performance under typical conditions: vbat t =3.6v; vddio=3.3v; t emp . : 25c . table 7 - 2. transmitter performance parameter description min . typ . max . unit frequency 2,412 2,484 mhz output power (1) , on_transmit 802.11b 1mbps 19.5 dbm 802.11b 11mbps 20.5 802.11g 6mbps 19.5 802.11g 54mbps 17.5 802.11n mcs 0 18.0 802.11n mcs 7 15.5 tx power accuracy 1.5 (2) db carrier suppression 30.0 dbc harmonic output power 2nd - 33 dbm/mhz 3rd - 38 notes: 1. measured at 802.11 spec compliant evm/spectral mask. 2. measured at rf pin assuming 50? differential.
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 2 0 20 8 external interfaces atwilc1000b external interfaces include : ? i 2 c slave for control ? spi slave and sdio slave for control and data transfer ? spi master for external flash ? i 2 c master for external eeprom ? t wo uart s for debug, control, and data tr ansfer ? general purpose input/ ou tput (gpio) pins ? wi - fi/ b luetooth coexistence interface with the exception of the spi slave and sdio slave host interfaces, which are selected using the dedicated sdio_spi_cfg pin, the other interfaces can be assigned to various pins by programming the corres ponding pin mux ing control register for each pin to a spec ific value between 0 and 6.the default values of these registers are 0, which is gpio mode. the summary of the available interfaces and their corresponding pin mux settings is shown in table 8 - 1 . for specific programming instructions , refer to atwilc1000b programming guide . table 8 - 1. pin - mux matrix of external interfaces 8.1 i 2 c slave interface the i 2 c slave interface, used primarily for control by the host processor, is a two - wire serial interface consisting of a serial data line (sda, pin 33) and a serial clock (scl, pin 32). it responds to the seven bit address value 0x60. the atwilc1000b i 2 c suppor ts i 2 c bus version 2.1 - 2000 and can operate in standard mode (with data rates up to 100 kb/s) and fast mo de (with data rates up to 400 kb/s). the i 2 c slave is a synchronous serial interface. the sda line is a bidirectional signal and changes only while the scl line is low, except for stop, start, and restart conditions. the output drivers are open - drain to perform wire - and functions on the bus. the maximum number of devices on the bus is limited by only the maximum c apacitance specification of 400 pf. data i s transmitted in byte packages. for specific information, refer to the philips specification entitled the i 2 c - bus specification, version 2.1. the i 2 c slave timing is provided in figure 8 - 1 and table 8 - 2 .
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 2 1 21 figure 8 - 1. i 2 c slave timing diagram table 8 - 2. i 2 c slave timing parameters parameter symbol min . max . units remarks scl clock frequency f scl 0 400 khz scl low pulse width t wl 1.3 s scl high pulse width t wh 0.6 scl, sda fall time t hl 300 ns scl, sda rise time t lh 300 this is dictated by external components start setup time t susta 0.6 s start hold time t hdsta 0.6 sda setup time t sudat 100 ns sda hold time t hddat 0 slave and master default 40 master programming op tion stop setup time t susto 0.6 s bus free time between stop and start t buf 1.3 glitch pulse reject t pr 0 50 ns 8.2 i 2 c master interface atwilc1000b provides an i 2 c bus master, which is intended primarily for accessing an external eeprom memory through a software - defined protocol. the i 2 c master is a two - wire serial interface consisting of a serial data line (sda) and a serial clock line (scl). sda can be configured on one of the following pins: sd_clk (pin 19), gpio1 (pin 24), gpio6 (pin 31), or i2c_sda (pin 33). scl can be configured on one of the following pins: gpio0 (pin 10), sd_dat3 (pin 12), gpio4 (pin 29), o r i2c_scl (pin 32). for more specific instructions refer to atwilc1000b programming guide. the i 2 c master interface supports three speeds: ? standard mode (100kb/s) ? fast mode (400kb/s) ? high - speed mode (3.4mb/s) t h l s d a s c l t h d s t a t w l t w h t s u d a t t p r t h d d a t t p r t p r t l h t h l t l h t s u s t o t b u f t s u s t a f s c l
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 2 2 22 the timing diagram of the i 2 c master interface is the same as that of the i 2 c slave interface (see figure 8 - 1 ). the timing parameters of i 2 c master are shown in table 8 - 3 . table 8 - 3. i 2 c master timing parameters parameter symbol standard mode fast mode high - speed mode units min . max . min . max . min . max . scl clock frequency f scl 0 100 0 400 0 3400 khz scl low pulse width t wl 4.7 1.3 0.16 s scl high pulse width t wh 4 0.6 0.06 scl fall time t hlscl 300 300 10 40 ns sda fall time t hlsda 300 300 10 80 scl rise time t lhscl 1000 300 10 40 ns sda rise time t lhsda 1000 300 10 80 start setup time t susta 4.7 0.6 0.16 s start hold time t hdsta 4 0.6 0.16 sda setup time t sudat 250 100 10 ns sda hold time t hddat 5 40 0 70 stop setup time t susto 4 0.6 0.16 s bus free time between stop and start t buf 4.7 1.3 glitch pulse reject t pr 0 50 8.3 spi slave interface atwilc1000b provides a serial peripheral interface (spi) that operates as a spi slave. the spi slave interface can be used for control and for serial i/o of 802.11 data. the spi slave pins are mapped as shown in table 8 - 4 . the rxd pin is same as master output, slave input (mosi), and the txd pin is same as master input, slave output (miso). the spi slave is a full - duplex slave - synchronous seria l interface that is available immediately following reset when pin 9 (sdio_spi_cfg) is tied to vddio . table 8 - 4. spi slave interface pin mapping pin # spi function 9 cfg: must be tied to vddio 16 ssn: active low slave select 18 sck: serial clock 13 rxd: serial data receive (mosi) 17 txd: serial data transmit (miso) when the spi is not selected, i.e., when ssn is high, the spi interface will not interfere with data transfers between the serial - master and other serial - slave devices. when the serial slave is not selected, its transmitted data output is buffered, resulting in a high impedance drive onto the serial master receive line.
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 2 3 23 the spi slave interface responds to a protocol that allows an external host to read or write any register in the chip as well as in itiate dma transfers. for the details of the spi protocol and more specific instructions refer to atwilc1000b programming guide. the spi slave interface supports four standard modes as determined by the clock polarity (cpol) and clock phase (cpha) settings . these modes are illustrated in table 8 - 5 and figure 8 - 2 . the red lines in figure 8 - 2 correspond to clock phase = 0 and the blue lines correspond to clock phase = 1. table 8 - 5. spi slave modes mode cpol cpha 0 0 0 1 0 1 2 1 0 3 1 1 figure 8 - 2. spi slave clock polarity and clock phase timing the spi slave timing is provided in figure 8 - 3 and table 8 - 6 . z z z z s c k c p o l = 0 c p o l = 1 s s n r x d / t x d ( m o s i / m i s o ) c p h a = 0 c p h a = 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 1 8
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 2 4 24 figure 8 - 3. spi slave timing diagram table 8 - 6. spi slave timing parameters parameter symbol min . max . units clock input frequency f sck 48 mhz clock low pulse width t wl 5 ns clock high pulse width t wh 5 clock rise time t lh 5 clock fall time t hl 5 input setup time t isu 5 input hold time t ihd 5 output delay t odly 0 20 slave select setup time t sussn 5 slave select hold time t hdssn 5 8.4 spi master interface atwilc1000b provides a spi master in terface for accessing external f lash memory. the spi master pins are mapped as shown in table 8 - 7 . the txd pin is same as master output, slave input (mosi), and the rxd pin is same as master input, slave output (miso). the spi master interface supports all four standard modes of clock pol arity and clock phase shown in table 8 - 5 . external spi f lash memory is accessed by a processor programming commands to the spi master interface, which in turn initi a tes a spi master access to the f lash. for more specific instructions refer to atwilc1000b programming guide .
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 2 5 25 table 8 - 7. spi master interface pin mapping pin # pin name spi function 28 gpio3 sck: serial clock output 29 gpio4 sck: active low slave select output 30 gpio5 txd: serial data transmit output (mosi) 31 gpio6 rxd: serial data receive input (miso) the spi master timing is provided in figure 8 - 4 and table 8 - 8 . figure 8 - 4. spi master timing diagram table 8 - 8. spi master timing parameters parameter symbol min . max . units clock output frequency f sck 48 mhz clock low pulse width t wl 5 ns clock high pulse width t wh 5 clock rise time t lh 5 clock fall time t hl 5 input setup time t isu 5 input hold time t ihd 5 output delay t odly 0 5 8.5 sdio slave interface the atwilc1000b sdio slave is a full speed interface. the interface supports the 1 - bit/4 - bit sd transfer mode at the clock range of 0 - 50mhz. the host can use this interface to read and write from any register within the chip as well as configure the atwilc1000b for data dma. to use this interface, pin 9 (sdio_spi_cfg) must be grounded. the sdio slave pins are mapped as shown in table 8 - 9 . f s c k t w h t l h t h l t w l t o d l y t i s u t i h d s c k s s n , t x d r x d
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 2 6 26 table 8 - 9. sdio interface pin mapping pin # spi f unction 9 cfg: must be tied to ground 12 dat3: data 3 13 dat2: data 2 16 dat1: data 1 17 dat0: data 0 18 cmd: command 19 clk: clock when the sdio card is inserted into an sdio aware host, the detection of the card will be via the means described in sdio specification. during the normal initialization and interrogation of the card by the host, the card will identify itself as an sdio device. the host software will obtain the card information in a tuple (linked list) format and determine if that cards i/o function(s) are acceptable to activate. if the card is acceptable, it will be allowed to power up fully and start the i/o function(s) built int o it. the sd memory card communication is based on an advanced 9 - pin interface (clock, command, four data , and three power lines) designed to operate at maximum operating frequency of 50mhz. the sdio slave interface has the following features: ? meets sdio c ard specification version 2.0 ? host clock rate variable between 0 and 50mhz ? 1 bit/4 - bit sd bus modes supported ? allows card to interrupt host ? responds to direct read/write (io52) and extended read/ write (io53) transactions ? supports suspend/resume operation t he sdio slave interface timing is provided in figure 8 - 5 and table 8 - 10 . figure 8 - 5. sdio slave timing diagram table 8 - 10. sdio slave timing parameters parameter symbol min . max . units clock input frequency f pp 0 50 mhz clock low pulse width t wl 10 ns s d _ c l k i n p u t s o u t p u t s f p p t w l t w h t h l t l h t i s u t i h t o d l y ( m a x ) t o d l y ( m i n )
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 2 7 27 parameter symbol min . max . units clock high pulse width t wh 10 clock rise time t lh 10 clock fall time t hl 10 input setup time t isu 5 input hold time t ih 5 output delay t odly 0 14 8.6 uart atwilc1000b has two universal asynchronous receiver/transmitter (uart) interface s for serial communication : uart1 and uart2 . the uart s are compatible with the rs - 232 standard, where atwilc1000b operates as d ata terminal equipment (dte). uart1 has a 2 - pin interface without flow control (rxd/txd) , where rxd (received data) can be enabled on one of five alternative pins and txd (transmitted dat a) can be enabled on one of seven alternative pins by programming their corresponding pin mux control registers (see table 8 - 1 ). uart2 has a 4 - pin interface with fl ow control (rxd/txd/cts/rts), where rxd (received data) can be enabled on one of two alternative pins, txd (transmitted data) can be enabled on one of two alternative pins, cts (clear to send) can be enabled on one of two alternative pins, and rts (request to send) can be enabled on one of two alternative pins by programming their corresponding pin mux control registers (see table 8 - 1 ). the rts and cts are used for hardware flow control; they must be connected to the host mcu uart and enabled for the uart interface to be functional. both uart s feature programmable baud rate generation with fractional clock division, which allows transmission and reception at a wide v ariety of standard and non - standard baud rates. the uart input clock is selectable between xo2, xo, xo2, and xo4, which corresponds to 52 mhz, 26 mhz, 13 mhz, and 6.5 mhz for the typical xo frequency (26mhz) . the clock divider value is programmable as 13 in teger bits and 3 fractional bits (with 8.0 being the smallest recommended value for normal operation). this results in the maximum baud rate of 52 mhz/8.0 = 6. 5 mbd for typical xo frequency. both uart s can be configured for seven or eight bit operation, with or without parity, with four different parity types (odd, even, mark, or space), and with one or two stop bits. they also have rx and t x fifos, which ensure reliable high speed reception and low software overhead transmission . fifo size is 4x 8 for both rx and tx direction. the uart s also ha ve status registers showing the number of received characters available in the fifo and various error conditions, as well the ability to generate interrupts based on these status bits. uart2 supports standard flow contro l using cts and rts signals C uart2 can be programmed to enable or disable flow control . cts is an active low input. when it is asserted (low) uart2 will transmit data; when it becomes de - asserted (high) uart2 will finish transmitting the current byte (if it is in progress) and will not resume transmitting until cts becomes asserted again. rts is an active low output. it becomes asserted (low) when the r x fifo in uart2 has space; it becomes de - asserted (high) when there is not enough space in the r x fifo. a n example of uart receiving or transmitting a single packet is shown in figure 8 - 6 . this example shows 7 - bit data (0x45), odd parity, and two stop bits. for more specific instructions refer to atwilc1000b programming guide.
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 2 8 28 figure 8 - 6. example of uart r x or t x packet 8.7 wi - fi/bluetooth coexistence atwilc1000b supports 2 - wire and 3 - wire wi - fi/bluetooth coexistence signaling conforming to the ieee 802.15.2 - 2003 standard, part 15.2. the type of coexistence interface used (2 or 3 wire) is chosen to be compatible with the specific bluetooth device used in a given application. coexistence interface can be enabled on several alternative pins by program ming their corresponding pin mux control register to 6 (see table 8 - 1 , where any pin marked io_coe in the mux6 column can be configured for any function of the coexistence interface) . table 8 - 11 shows a usage example of the 2 - wire interface using the gpio3 and gpio4 pins; 3 - wire interface using the gpio3, gpio4, and gpio5 pins; f or more specific instructions on configuring coexistence refer to atwilc1000b programming guide . table 8 - 11. coexistence pin assignment example pin n ame pin # function target 2 - wire 3 - wire gpio3 28 bt_req bt is requesting to access the medium to trans- mit or receive. goes high on tx or rx slot used used gpio4 29 wl_act device response to the bt request. high - bt_req is denied and bt slot blocked. used used gpio5 30 bt_pri priority of the bt packets in the requested slot. high to indicate high priority and low for normal. not used used gpio6 31 ant_sw direct control on antenna (coex bypass) optional optional 8.8 gpios nine general purpose input/ output (gpio) pins, labeled gpio 0 - 8, are available to allow for application specific functions. each gpio pin can be programmed as an input (the value of the pin can be read by the host or internal processor) or as an output (the output values can be programmed by the host or internal processor), where the default mode after power - up is input. gpios 7 and 8 are only available when the host doe s not use the sdio interface, which shares two of its pins with these gpios. therefore, for sdio - based applications, seven gpios (0 - 6) are available. for more specific usage instructions refer to atwilc1000b programming guide .
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 2 9 29 9 power management 9.1 power architecture atwilc1000b uses an innovative power architecture to eliminate the need for external regulators and reduce the number of off - chip components. this architecture is shown in figure 9 - 1 . the power management unit (pmu) has a dc/dc converter that converts vbatt to the core supply used by the digital and rf/ams blocks. table 9 - 1 shows the typical values for the digital and rf /ams core voltages. the pa and e fuse are supplied by dedicated ldos, and the vco is supplied by a separate ldo structure . figure 9 - 1. power architecture
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 3 0 30 table 9 - 1. pmu output voltages parameter typical rf/ams core voltage (vreg_buck) 1.35v digital core voltage (vddc) 1.10v the power connections in figure 9 - 1 provide a conceptual framework for understanding the atwilc1000b power architecture. r efer to the reference design for an example of power supply connections, including proper isolation of th e supplies used by the digital and rf/ams blocks . 9.2 power consumption 9.2.1 description of device states atwilc1000b has several devices states: ? on_transmit C device is actively transmitting an 802.11 signal . highest output power and nominal current consumption ? on _receive C device is actively receiving an 802.11 signal . lowest sensitivity and nominal current consumption ? on_doze C device is on but is neither transmitting nor receiving ? power_down C device core supply off (leakage) the following pins are used to switch between the on and power_down states: ? chip_en C device pin (pin #23) used to enable dc/dc converter ? vddio C i/o supply voltage from external supply in the on states, vddio is on and chip_en is high (at vddio voltage le vel). to switch between the on states and power_down state chip_en has to change between high and low (gnd) voltage. when vddio is off and chip_en is low, the chip is powered off with no leakage (also see section 9.2 .3 ). 9.2.2 current consumption in various device states table 9 - 2. current consumption device state code rate output power, dbm current consumption ( 1 ) i vbatt i vddio on_transmit 802.11b 1mbps 19.5 294 ma 22ma 802.11b 11mbps 20.5 290 ma 22ma 802.11g 6mbps 19.5 292ma 22ma 802.11g 54mbps 17.5 250 ma 22 ma 802.11n mcs 0 18.0 289 ma 22 ma 802.11n mcs 7 15.5 244 ma 22 ma on_receive 802.11b 1mbps n/a 52.5ma 22 ma 802.11b 11mbps n/a 52.5ma 22 ma 802.11g 6mbps n/a 55.0 ma 22 ma 802.11g 54mbps n/a 57.5 ma 22ma 802.11n mcs 0 n/a 54.0 ma 22ma
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 3 1 31 device state code rate output power, dbm current consumption ( 1 ) i vbatt i vddio 802.11n mcs 7 n/a 58.5 ma 22ma on_doze n/a n/a 3 80a <10a power_down n/a n/a <0.5a <0.2a note: 1. conditions: vbat t @3.6v, vdd io @ 2 .8v , 25c 9.2.3 restrictions for power states when no power supplied to the device , for example, the dc/dc converter output and vddio are both off (at ground potential) , a voltage cannot be applied to the device pins because each pin contains an esd diode from the pin to supply. this diode will turn on when v oltage higher than one diode - drop is supplied to the pin. if a voltage must be applied to the signal pads while the chip is in a low power state, the vddio supply must be on, so the sleep or power_down state must be used. similarly, to prevent the pin - to - g round diode from turning on, do not apply a voltage that is more than one diode - drop below ground to any pin. 9.3 power - up/d own sequence the power - up/down sequence for atwilc1000b is shown in figure 9 - 2 . the timing parameters are provided in table 9 - 3 . figure 9 - 2. power up/down sequence table 9 - 3. power - up/down sequence timing parameter min . max . unit description notes t a 0 ms vbatt rise to vddio rise vbatt and vddio can rise simultaneously or can be tied together. vddio must not rise before vbatt. t b 0 vddio rise to chip_en rise chip_en must not rise before vddio. chip_en must be driven high or low, not left floatin g. v b a t t v d d i o c h i p _ e n r e s e t n t a t b t c x o c l o c k t b ' t a ' t c '
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 3 2 32 parameter min . max . unit description notes t c 5 chip_en rise to resetn rise this delay is needed because xo clock must stabilize before resetn removal. resetn must be driven high or low, not left floating. t a 0 vddio fall to vbatt fall vbatt and vddio can fall simultaneously or can be tied together. vbatt must not fall be- fore vddio. t b 0 chip_en fall to vddio fall vddio must not fall before chip_en. chip_en and resetn can fall simultane- ously. t c 0 resetn fall to vddio fall vddio must not fall before resetn. re- setn and chip_en can fall simultaneously. 9.4 digital i/o pin behavior during power - up sequences the following table represents digital i / o pin states corresponding to device power modes . table 9 - 4. digital i/o pin behavior in different device states device state vddio chip_en resetn output driver input driver pull up/down resistor (96k?) power_down: core supply off high low low disabled (hi - z) disabled disabled power - on reset: core supply on, hard reset on high high low disabled (hi - z) disabled enabled power - on default: core supply on, device out of reset but not programmed yet high high high disabled (hi - z) enabled enabled on_doze/ on_transmit/ on_receive: core supply on, device pro- grammed by firmware high high high programmed by firmware for each pin: enabled or disabled opposite of output driver state programmed by firmware for each pin: enabled or disabled
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 3 3 33 10 reference design the atwilc1000b reference design schematic is shown in figure 10 - 1 . figure 10 - 1. atwilc10 00b reference schematic vddc vddc 1p3v vddio vbat vddio vddio vddio place c2 next to pin 3. place c11 next to pin 37. place c1 next to pins 2 & 4. place c19 next to pin 38. l2 0 r20 4.7k r19 4.7k r5 0 r8 0 r6 0 r12 0 r13 0 r14 0 place c8 & c12 next to pins 14 & 27 place c4, c5 and c6 next to pins 15, 26 & 39 vbat vbat vddio vddio c8 2.2uf c12 2.2uf 0 ohm resistors are placeholders in case f ilter resistors are required to reduce rf noise. antenna matching network. place right next to antenna low pass filter for harmonics external 32.768khz clock may be used instead of on chip sleep clock. (use rtc pin). l5 = 15nh is required in series with l1 = 1uh to reduce switching noise rf interf erence. connect chip_en and resetn to host gpio pins that def ault low or high impedance with a pull down resistor at power on. values shown are initial v alues f or cry stal cl=8pf but must be adjusted f or each board design. c2 2.2uf wlan_wake required if uart is the only host interf ace used. if spi or sdio is used, wake pin is not required and should be lef t unconnected. c11 2.2uf sd_dat2 sd_dat3 sd_cmd sd_dat0 sd_dat1 sd_clk txd rxd c19 0.1uf c1 0.01uf fb2 blm03ag121sn1 1 2 fb1 blm03ag121sn1 1 2 c21 dni r3 dni c16 6.8pf l8 3.3nh c17 1.0pf y1 26mhz r11 0 c7 1.0uf c3 2.2uf 6.3v c23 6.8pf l1 1uh fb3 blm03ag121sn1 1 2 e1 antenna l3 2.0nh c5 0.1uf r17 0 c4 0.1uf c10 2.2uf 6.3v l9 3.3nh c33 0.7pf r16 0 u1 atwilc1000 tpp 1 vddrf_rx 2 rfiop 7 rfion 8 vdd_rf_tx 4 vbat_pa 6 vdd_ams 3 vbat_ppa 5 sdio_spi_cfg 9 wake 10 irqn 11 sd_dat3 12 sd_dat2_spi_rxd 13 vddc1 14 vddio_0 15 sd_dat1_spi_ssn 16 sd_dat0_spi_txd 17 sd_cmd_spi_sck 18 sd_clk 19 vbat_buck 20 vsw 21 chip_en 23 vreg_buck 22 rtc_mux 24 test_mode 25 vddio_1 26 vddc2 27 gpio_3 28 gpio_4 29 gpio_5 30 gpio_6 31 i2c_scl 32 i2c_sda 33 resetn 34 xo_n 35 xo_p 36 vdd_sxdig 37 vdd_vco 38 vddio_a 39 tpn 40 vss 41 c24 6.8pf r2 0.5pf l5 15nh r18 0 c22 dni c15 6.8pf c32 1.0pf c6 0.1uf wlan_wake irqn reset_n chip_en i2c_scl i2c_sda 1p3v
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 3 4 34 11 reflow profile information this section provides guidelines for reflow processes in getting the atmel module sold ere d to the customers design. 11.1 storage condition 11.1.1 moisture barrier bag before opened a moisture barrier bag must be stored in a temperature of less than 30 c with humidity under 85% rh. the calculated shelf life for the dry - packed product shall be 12 months fr om the date the bag is sealed. 11.1.2 moisture barrier bag open humidity indicator cards must be blue, < 30%. 11.2 stencil design the recommended stencil is laser - cut, stainless - steel type with thickness of 100m to 130m and approximately a 1:1 ratio of stencil openin g to pad dimension. to improve paste release, a positive taper with bottom opening 25m larger than the top can be utilized. local manufacturing experience may find other combinations of stencil thickness and aperture size to get good results. 11.3 baking condi tions this module is rated at msl level 3. after sealed bag is opened, no baking is required within 168 hours so long a s the devices are held at 30 o c/60% rh or stored at <10% rh. the module will require baking before mounting if: ? the sealed bag has been o pen for >168 hours ? humi dity indicator card reads >10% ? sips need to be baked for 8 hours at 125 c 11.4 soldering and reflow condition 11.4.1 reflow oven it is strongly recommended that a reflow oven equipped with more heating zones and nitrogen atmosphere be used for lead - free assembly. nitrogen atmosphere has shown to improve the wet - ability and reduce temperature gradient across the board. it can also enhance the appearance of the solder joints by reducing the effects of oxidation. the following bullet items should a lso be o bserved in the reflow process: ? some recommended pastes include nc - smq ? 230 flux and indalloy ? 241 solder paste made up of 95.5 sn/3.8 ag/0.7 cu or senju n705 - grn33 60 - k2 - v type 3, no clean paste ? allowable reflow soldering times: 2 times based on the following reflow soldering profile (see figure 11 - 1 ) ? temperature profile: reflow soldering shall be done according to the following temperature pro file (see figure 11 - 1 ) ? peak temp: 250c
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 3 5 35 figure 11 - 1. solder reflow profile
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 3 6 36 12 reference documentation and support 12.1 reference documents atmel offers a set of col lateral documentation to ease integration and device ramp. the following list of documents available on atmel web or integrated into development tools. to enable fast development contact your local fae or visit the htt p://www.atmel.com/ . title content datasheet this document design files package user guide, schematic, pcb layout, gerber, bom & system notes on: rf/radio full test report, radiation pattern, design guide - lines, temperature performance, esd. platform getting started guide how to use package: out of the box starting guide, hw limitations and notes, sw quick start guidelines . hw design guide best practices and recommendations to design a board with the product, including: antenna design for wi - fi (layo u t recommendations, types of an tennas, impedance matching, using a power amplifier , etc . ), spi/uart protocol between wi - fi soc and the host mcu. sw design guide integration guide with clear description of: high level arch, overview on how to write a networking application, list all api, parameters and structures. features of the device, spi/handshake protocol between device and host mc u, flow/se- quence/state diagram and timing. sw programmer g uide explain in details the flow chart and how to use each api to implement all generic use cases (e.g. start ap, start sta, provisioning, udp, tcp, http, tls, p2p, errors manage- ment, connection/transf er recovery mechanism/state dia gram) - usage and sample app note . for a complete listin g of development - support tools and documentation, visit http://www.atmel.com/ , o r contact the nearest atmel field representative.
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 3 7 37 13 revision history doc rev. date comments 42491 b 03 /2016 1. update package drawings in figures figure 3 - 2 and figure 3 - 3 . 2. clarified the datapath description in sectio n 7.1.2 . 3. revise transmit power table values in table 7 - 2 . 4. updated power consumption table values in table 9 - 2 . 5. updated schematic figure to rev 2 in figure 10 - 1 . 6. include reflow profile data in chapter 11 . 42491 a 0 7 / 2015 ds update to revb offering changes from wilc1000 a (42351c) to wilc1000 b : 1. added second uart, increased uart data rates 2. increased instruction ram size from 128kb to 160kb 3. updated pin mux table: added new options for various interfaces 4. improved description of coexistence interface 5. added vdd_vco switch and connection in the power architecture 6. updated power consumption numbers 7. updated reference schematic 8. changed rtc_clk pad definition from pull - down to pull - up 9. modified sections 9.2.1 and 9.2.2 to add high - power and low - power modes and cur- rent consumption numbers 10. updated radio performance in table 7 - 1 and table 7 - 2 11. fixed typos for spi slave interface timing in table 8 - 6 12. fixed typos for battery supply name: changed from vbat to vbatt 13. corrected table 8 - 11 14. corrected doze mode current in table 9 - 2 and in feature list 15. corrected table 4 - 3 and added high - drive pads reference in table 3 - 1 16. miscellaneous minor updates and corrections
atwilc1000b - mut [ datasheet ] atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 3 8 38 atmel corporation 1600 technology drive, san jose, ca 95110 usa t: (+1)(408) 441.0311 f: (+1)(408) 436.4200 www.atmel.com ? 2016 atmel corporation. / rev.: atmel - 42491 b - atwilc1000b - mut_datasheet_03/2016 . atmel ? , atmel logo and combinations thereof, enabling unlimited possibilities ? , and others are registered trademarks or trademarks of atmel corporation in u.s. and other countries. other terms and product na mes may be trademarks of others. disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, b y estoppel or otherwise, to any intellectual property right is granted by this document or in connection wi th the sale of atmel products. except as set forth in the atmel terms and conditions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, b ut not limited to, the implied warranty of merchantability, fitness for a particular purpose, or non - infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without li mita tion, damages for loss and profits, business interruption, or loss of information) arising out of the use or inability to use this document , even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties wit h respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. atmel does not make any commitment to update the information contained herein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive app lications. atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. safety - critical, military, and automotive applications disclaimer: atmel products are not designed for and will not be used in conne ction with any applications where the failure of such products would reasonably be expected to result in sign ificant personal injury or death (safety - critical applications) without an atmel officer's specific written consent. safety - critical applications include, without limitation, life support devices and systems, equipment or systems for the operation o f nuc lear facilities and weapons systems. atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically desi gnated by atmel as military - grade. atmel products are not designed nor intended for use in automotive applications unless specifically designated by atmel as automotive - grade.

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